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GK One-Line Question & Answer

15541+ short questions with short answers, covering every category and sub-category on the site — no long articles to scroll through. Good for a fast recap before an exam, or a few minutes of daily practice.

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Computer Fundamentals → Introduction to Computer 33

Which memory technology uses phase change (crystalline vs amorphous)?
Phase Change Memory (PCM/3D XPoint)
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Compute Express Link (CXL) is?
High-speed interconnect enabling cache-coherent CPU-accelerator-memory communication
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Die stacking (3D IC) in chip design?
Stacks multiple chips vertically with through-silicon vias (TSV) for density
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Chiplet design disaggregates?
Monolithic chip into smaller, specialized dies connected via interconnect
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AMD EPYC processors use chiplet design with?
Multiple CPU chiplets + I/O die connected via Infinity Fabric
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EUV (Extreme Ultraviolet) lithography uses light at wavelength of?
13.5 nm
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FinFET transistor structure has?
Vertical fin-shaped channel for better gate control
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GAA (Gate All Around) FET improves on FinFET by?
Surrounding the channel on all four sides for better control at smaller nodes
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Process node (e.g., 7nm) in chip manufacturing refers to?
Marketing term roughly corresponding to transistor density
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Photolithography in chip manufacturing?
Uses light to transfer circuit patterns from mask to wafer
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Which company manufactures chips for Apple Silicon?
TSMC (Taiwan Semiconductor Manufacturing Company)
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Moore's Law is expected to slow down because?
Physical limits of silicon at atomic scale
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Beyond Moore's Law innovations include?
Chiplets, 3D stacking, new materials (GaN, SiC, 2D materials), neuromorphic
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RISC-V is notable because?
Open, royalty-free instruction set architecture for custom processor design
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ARM vs x86: ARM dominates mobile because?
Higher performance per watt
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Apple Silicon (M1/M2/M3) is based on?
ARM architecture with custom Apple-designed cores
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Heterogeneous computing uses?
Mix of processors (CPU+GPU+NPU+DSP) for optimal efficiency
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NPU (Neural Processing Unit) in smartphones optimizes?
AI inference workloads using dedicated neural network hardware
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DSP (Digital Signal Processor) is optimized for?
Real-time signal processing (audio, radio, sensor data)
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Memory controller integration into CPU (IMC) was pioneered by?
AMD with Opteron/Athlon 64 (2003)
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Simultaneous Multi-Threading (SMT) increases?
CPU throughput by filling pipeline stalls with another thread's instructions
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Branch misprediction penalty causes?
Pipeline flush — wasted cycles on wrong-path instructions
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Tomasulo's algorithm implements?
Out-of-order execution with register renaming to eliminate false dependencies
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Superscalar processor can issue how many instructions per clock?
Multiple (2-8 per cycle)
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VLIW (Very Long Instruction Word) architecture?
Compiler explicitly specifies multiple parallel operations in one wide instruction
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Which processor feature reduces memory latency for pointer chasing?
Both A and B
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Power gating in processors?
Cuts power to unused circuit blocks to save energy
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DVFS (Dynamic Voltage and Frequency Scaling)?
Adjusts CPU voltage and frequency based on workload to balance performance/power
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Turbo Boost (Intel) / Precision Boost (AMD) allows CPUs to?
Temporarily exceed rated base clock when thermal/power headroom exists
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Load-Store architecture (RISC) means?
Only LOAD and STORE instructions access memory — ALU operations use registers
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Which memory ordering is required by x86?
Total Store Order (TSO) — strong consistency guarantees
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Memory fence/barrier instruction ensures?
Memory operations before fence complete before those after fence
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std::atomic in C++11 provides?
Lock-free thread-safe operations with specified memory ordering
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Computer Fundamentals → Memory Units 6

Resistive RAM (ReRAM/RRAM) stores data using?
Variable resistance of a dielectric material
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Magnetoresistive RAM (MRAM) uses?
Magnetic tunnel junction resistance for non-volatile storage
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Ferroelectric RAM (FeRAM) stores data using?
Polarization of ferroelectric material (non-volatile, fast, low power)
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Which bus is used for connecting DRAM to the memory controller in modern systems?
DDR bus (parallel, point-to-point)
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Register renaming eliminates which data hazard?
WAR and WAW hazards (false dependencies)
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Which instruction determines if two registers are equal (RISC-V)?
BEQ
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Computer Fundamentals → Software and Hardware 1

Which C/C++ keyword prevents compiler reordering of memory operations?
volatile
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