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GK One-Line Question & Answer

15541+ short questions with short answers, covering every category and sub-category on the site — no long articles to scroll through. Good for a fast recap before an exam, or a few minutes of daily practice.

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Computer Fundamentals → Introduction to Computer 37

Which microarchitecture technique hides memory latency?
Out-of-order execution with many in-flight memory operations
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Store-to-Load forwarding allows?
A load to receive its value from a recent pending store before it writes to cache
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Micro-ops (uops) in x86 are?
Simpler internal operations that x86 instructions are decoded into
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Decoded ICache (DSB in Intel) stores?
Pre-decoded uops to avoid re-decoding hot loops
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Loop Stream Detector (LSD) in Intel CPUs?
Recognizes small loops and serves uops directly from loop buffer
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Meltdown vulnerability exploits?
Speculative execution allowing reading kernel memory from user space
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Spectre vulnerability exploits?
Branch prediction to leak data via cache side channels
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Rowhammer attack exploits?
DRAM physical cell crosstalk — repeated access flips bits in nearby rows
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Which performance counter measures CPU cycles?
CPU_CLK_UNHALTED (cycles)
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IPC (Instructions Per Cycle) measures?
How many instructions the CPU completes per clock cycle
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CPI (Cycles Per Instruction) is?
1/IPC
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Which tool profiles CPU performance counters on Linux?
perf
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Cache line size on modern x86 CPUs is typically?
64 bytes
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False sharing mitigation strategy includes?
Padding data structures to separate hot variables to different cache lines
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NUMA-aware memory allocation uses?
Allocate memory on the NUMA node closest to the thread
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PCIe peer-to-peer (P2P) allows?
Two PCIe devices to transfer data directly without CPU involvement
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NVMe over Fabrics (NVMe-oF) extends NVMe?
Over network (RDMA, FC, TCP) for disaggregated storage with NVMe latency
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RDMA (Remote Direct Memory Access) allows?
Network adapter to directly read/write remote memory — bypassing remote CPU
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RoCE (RDMA over Converged Ethernet) provides?
RDMA capability over standard Ethernet infrastructure
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Which memory bus standard replaced the dedicated front-side bus?
QPI/UPI (Intel) and HyperTransport (AMD)
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Intel UPI (Ultra Path Interconnect) connects?
Multiple CPUs in multi-socket servers
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Power consumption breakdown in modern CPUs: dynamic power scales with?
CV²f (Capacitance × Voltage² × frequency)
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Leakage current in transistors becomes dominant at?
Small process nodes (sub-22nm) — significant even when transistor is off
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Which technology reduces power in CPUs by temporarily stopping clock signal to idle blocks?
Clock gating
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Adiabatic computing attempts to?
Recover energy from computation rather than dissipating it as heat
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HBM (High Bandwidth Memory) is connected to the GPU/CPU via?
Through Silicon Via (TSV) on the same package (2.5D/3D)
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2.5D integration uses?
Dies placed side-by-side on a silicon interposer connected by short interconnects
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Which memory has the lowest latency?
SRAM (on-die cache)
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Crossbar switch in memory systems allows?
Any input to connect to any output simultaneously — O(n²) connections
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Directory-based cache coherence scales better than snooping because?
Reduces broadcast traffic — messages sent only to relevant nodes
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Write-invalidate vs write-update cache protocol: write-invalidate?
Invalidates all other copies when one core writes — most common today
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Which cache coherence protocol state allows only one cache to have a dirty copy?
Modified (M) state in MESI
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Which layer of OSI model deals with node-to-node data delivery?
Data Link layer
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Which protocol is connection-oriented at Layer 4?
TCP
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Which field in IPv4 header identifies the upper-layer protocol?
Protocol field
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IPv4 fragmentation occurs when?
Packet size exceeds MTU of the path
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IPv6 handles fragmentation differently by?
Only source host fragments; routers do not
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Computer Fundamentals → Operating System Basics 2

KASLR (Kernel Address Space Layout Randomization) randomizes?
Kernel virtual address layout to mitigate exploits
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Kernel Page Table Isolation (KPTI/KAISER) mitigates?
Meltdown by separating kernel and user page tables
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Computer Fundamentals → Memory Units 1

SRAM vs DRAM speed: SRAM is faster because?
No refresh needed — flip-flop based storage with no capacitor discharge
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