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GK One-Line Question & Answer

15541+ short questions with short answers, covering every category and sub-category on the site — no long articles to scroll through. Good for a fast recap before an exam, or a few minutes of daily practice.

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Computer Fundamentals → Introduction to Computer 34

RISC-V is notable because?
Open, royalty-free instruction set architecture for custom processor design
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ARM vs x86: ARM dominates mobile because?
Higher performance per watt
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Apple Silicon (M1/M2/M3) is based on?
ARM architecture with custom Apple-designed cores
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Heterogeneous computing uses?
Mix of processors (CPU+GPU+NPU+DSP) for optimal efficiency
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NPU (Neural Processing Unit) in smartphones optimizes?
AI inference workloads using dedicated neural network hardware
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DSP (Digital Signal Processor) is optimized for?
Real-time signal processing (audio, radio, sensor data)
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Memory controller integration into CPU (IMC) was pioneered by?
AMD with Opteron/Athlon 64 (2003)
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Simultaneous Multi-Threading (SMT) increases?
CPU throughput by filling pipeline stalls with another thread's instructions
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Branch misprediction penalty causes?
Pipeline flush — wasted cycles on wrong-path instructions
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Tomasulo's algorithm implements?
Out-of-order execution with register renaming to eliminate false dependencies
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Superscalar processor can issue how many instructions per clock?
Multiple (2-8 per cycle)
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VLIW (Very Long Instruction Word) architecture?
Compiler explicitly specifies multiple parallel operations in one wide instruction
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Which processor feature reduces memory latency for pointer chasing?
Both A and B
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Power gating in processors?
Cuts power to unused circuit blocks to save energy
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DVFS (Dynamic Voltage and Frequency Scaling)?
Adjusts CPU voltage and frequency based on workload to balance performance/power
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Turbo Boost (Intel) / Precision Boost (AMD) allows CPUs to?
Temporarily exceed rated base clock when thermal/power headroom exists
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Load-Store architecture (RISC) means?
Only LOAD and STORE instructions access memory — ALU operations use registers
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Which memory ordering is required by x86?
Total Store Order (TSO) — strong consistency guarantees
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Memory fence/barrier instruction ensures?
Memory operations before fence complete before those after fence
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std::atomic in C++11 provides?
Lock-free thread-safe operations with specified memory ordering
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Which microarchitecture technique hides memory latency?
Out-of-order execution with many in-flight memory operations
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Store-to-Load forwarding allows?
A load to receive its value from a recent pending store before it writes to cache
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Micro-ops (uops) in x86 are?
Simpler internal operations that x86 instructions are decoded into
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Decoded ICache (DSB in Intel) stores?
Pre-decoded uops to avoid re-decoding hot loops
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Loop Stream Detector (LSD) in Intel CPUs?
Recognizes small loops and serves uops directly from loop buffer
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Meltdown vulnerability exploits?
Speculative execution allowing reading kernel memory from user space
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Spectre vulnerability exploits?
Branch prediction to leak data via cache side channels
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Rowhammer attack exploits?
DRAM physical cell crosstalk — repeated access flips bits in nearby rows
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Which performance counter measures CPU cycles?
CPU_CLK_UNHALTED (cycles)
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IPC (Instructions Per Cycle) measures?
How many instructions the CPU completes per clock cycle
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CPI (Cycles Per Instruction) is?
1/IPC
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Which tool profiles CPU performance counters on Linux?
perf
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Cache line size on modern x86 CPUs is typically?
64 bytes
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False sharing mitigation strategy includes?
Padding data structures to separate hot variables to different cache lines
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Computer Fundamentals → Memory Units 3

Which bus is used for connecting DRAM to the memory controller in modern systems?
DDR bus (parallel, point-to-point)
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Register renaming eliminates which data hazard?
WAR and WAW hazards (false dependencies)
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Which instruction determines if two registers are equal (RISC-V)?
BEQ
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Computer Fundamentals → Software and Hardware 1

Which C/C++ keyword prevents compiler reordering of memory operations?
volatile
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Computer Fundamentals → Operating System Basics 2

KASLR (Kernel Address Space Layout Randomization) randomizes?
Kernel virtual address layout to mitigate exploits
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Kernel Page Table Isolation (KPTI/KAISER) mitigates?
Meltdown by separating kernel and user page tables
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